The present invention relates to a method of manufacturing semiconductor device and, more particularly, to a method of manufacturing a reliable and highly integrated wiring.
FIG. 1 is a sectional view of two memory cells of a Dynamic Random Access Memory (DRAM). N-type diffusion regions 12 and 13 of storage capacitors and n-type diffusion region 14 of a selection transistor are formed on p-type semiconductor substrate 11. Capacitor electrodes 16 and 17 made of polysilicon are formed on insulating layers 15 overlying n-type diffusion regions 12 and 13. Word lines 19A and 19B made of polysilicon are formed on a part of semiconductor substrate 11 which is located between n-type diffusion region 12 and n-type diffusion region 14, and between n-type diffusion region 13 and n-type diffusion region 14, respectively. Word lines 19C and 19D of other memory cells are formed on capacitor electrodes 16 and 17, respectively, and insulating interlayer 23 is formed to cover the semiconductor structure. A contact hole 24 to the surface of n-type diffusion region 14 is formed in insulating interlayer 23, and bit line 25 is formed to connect with n-type diffusion region 14 through contact hole 24.
FIG. 2 shows an equivalent circuit of memory cells having the structure shown in FIG. 1. Each memory cell consists of a capacitor C and a selection transistor Q, each diffusion region of selection transistor Q is connected in common with a bit line BL, and a gate electrode of selection transistor Q is connected to respective word lines WL.
In the manufacturing method, since contact hole 24 is formed through insulating interlayer 23, it is necessary to allow a dimension margin L between word lines 19A and 19B to prevent any short circuit between each of word lines 19A and 19B and bit line 25. For example the dimension margin L needs must be about 1.0 .mu.m for a 1.0 .mu.m design rule device; therefore, according to conventional manufacturing methods, it is difficult to improve the microminiaturization of the structure.
To solve this problem, in another conventional method, the microminiaturization of the memory cell is realized by the method as shown in FIGS. 3(a)-3(c). In this method, after n-type diffusion regions 32 and 33 are formed on a p-type semiconductor substrate 31, insulation layer 34 and capacitor electrodes 35 and 36 are formed. A silicon dioxide layer, a polysilicon layer and a CVD silicon dioxide layer are formed on the semiconductor structure, successively, and are respectively formed into gate oxide layer 37; word lines 38A, 38B, 38C and 38D; and CVD silicon dioxide layers 39A, 39B, 39C and 39D by anisotropic etching (for example RIE (Reactive Ion Etching)). N-type diffusion region 40 of the selection transistor is formed by ion-implantation using word lines 38A, 38B, 38C and 38D as masks, at the same time all of n-type diffusion regions 32 and 33 are formed (FIG. 3(a)).
A CVD silicon dioxide layer is then formed on the whole surface, and antisotropicly etched to form CVD silicon dioxide and antisotropicly etched to form CVD silicon dioxide side walls of word lines 38A, 38B, 38C and 38D (FIG. 3(b)).
A CVD silicon dioxide layer is formed on the whole surface, and the portion of the just-formed CVD silicon dioxide layer which is located between word lines 38A and 38B is etched to form CVD silicon dioxide layer 43 having contact hole 42 to n-type diffusion region 40. Bit line 44 made of a polycide layer is then formed (FIG. 3(c)).
According to the method as described above, even if contact hole 42 is wide, word lines 38A, 38B, 38C and 38D covered with CVD silicon dioxide layer 43 cannot be etched. Thus, it is unnecessary to consider the superfluous dimension margin L and it is possible to improve the microminiaturization of the elements However, the memory cell formed by the method as described above exhibits a large difference in level across the surface thereof Breakage of bit line 44 on the corner of structure is thus apt to occur often.
To solve the problem described above, a method as shown in FIG. 4 is considered. In this method, before bit line 44 is formed, a silicate glass layer having a low melting point, for example BPSG (Boron Phosphorus Silicate Glass) layer 45, is formed on the whole surface and is flattened by thermal annealing. A contact hole is then formed through this layer. In this structure, thickness T1 of BPSG layer 45 above word lines 38A and 38B differs from that of thickness T2 of PBSG layer 45 above n-type diffusion region 40. Thus, when BPSG layer 45 is etched to form a contact hole for a bit line, there is the possibility that word lines 38A and 38B will be exposed, and a connection between one of the word lines and the bit line may be formed.
In the method as described above, it is possible to improve the microminiaturization of the elements, but opening of upper wiring is apt to occur often.